The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Advances in technology have led to a proliferation of intelligent devices. Such devices are equipped with one or more processors. The continuing drop in prices of memory has allowed device makers to equip their intelligent devices with program and storage memory having increasingly large footprints. In part, because of the availability of large memory sizes, sophisticated feature-rich, multi-threading operating systems (OS) power and control intelligent devices, etc. This has in part allowed device manufacturers to provide users of the devices with an improved user experience.
However, this has contributed to the increased complexity of the devices. Debugging, integrating, and testing such devices presents unique challenges because of the complexity of the device architecture and speed of operation. To determine the root cause of device failures during development and deployment of such devices requires the creation of sophisticated high speed debugging tools and methods.